1. Field of the Invention
This invention relates to a data transfer system for transferring data stored in a particular memory area in memory means to another memory area.
2. Description of the Prior Art
Heretofore, in an information processing apparatus or the like, when a rectangular area 2 toward SADD in the memory area in a memory unit 1, as shown, for example, in FIG. 1 of the accompanying drawings is to be transferred to a rectangular area 3 DADD, the transfer control shown below has been effected.
Referring to FIG. 2 of the accompanying drawings which is a block diagram of an information processing apparatus having a data transferring function, reference numeral 1 designates a memory unit, reference numeral 10 denotes a transfer control unit for controlling the address of the memory unit 1 during data transfer and the read-out/written-in data, reference numeral 11 designates a data control section for controlling the data in the transfer control unit, and reference numeral 12 denotes an address control section for controlling the address in the transfer control unit 10. Reference numeral 13 designates a central processing unit, and reference numeral 14 denotes an input/output unit.
The details of the data control section 11 are shown in FIG. 3 of the accompanying drawings.
In FIG. 3, reference numeral 20 designates an S register for storing therein the data read out from the rectangular area 2, reference numeral 25 denotes a shift unit for shifting the contents of S register 20 in accordance with the value of SH register 26, reference numeral 27 denotes a function register in which the logical operation (logical product, logical sum, exclusive logical sum, etc.) command for a function unit 30 is stored, reference numeral 28 designates a mask register, reference numeral 29 denotes a D register for storing therein the data read out from the rectangular area 3, reference numeral 30 designates a function unit for logically operating the values from the S register 20 and the D register 29 in accordance with a command indicated by the aforementioned function register, and reference numeral 31 denotes a selector for masking the output data from the function unit 30 and the output data from D register 29 by the masking information from the mask register 28 and outputting the same and writing the same into the rectangular area 3. This is for eliminating any unnecessary bits of the data read out from the memory unit 1 in a byte unit (or a word unit) by applying a mask thereto in order to effect data transfer in individual byte units.
A detailed block diagram of the address control section 12 is shown in FIG. 4 of the accompanying drawings.
In FIG. 4, reference numeral 40 designates an S selector, reference numeral 41 denotes an S address register for showing the read-out starting address of each line of the rectangular area 2, reference numeral 42 designates an S address counter for showing the memory access address of the rectangular area 2 of the memory unit 1 on the basis of the value of the S address register 41, reference numeral 43 denotes an S adder, reference numeral 44 designates an X register for showing the lateral length X of the rectangular area, reference numeral 45 denotes an X counter for detecting the termination of the transfer of the data corresponding to the lateral length X, reference numeral 46 designates a Y register for showing the vertical length Y of the rectangular area, reference numeral 47 denotes a Y counter for detecting the termination of the transfer of the data corresponding to the vertical length Y, namely, the termination of the transfer of all data, reference numeral 48 designates a timing circuit for effecting the read-out timing control of the memory unit 1, reference numerals 49 and 54 denote a SP register and a DP register, respectively, for showing the length of one line of the memory unit 1, reference numeral 50 designates a D selector, reference numeral 51 denotes a D address register for showing the read-out starting address of each line of the rectangular area 3, reference numeral 52 designates a D address counter for showing the memory access address of the rectangular area 3, and reference numeral 53 denotes a D adder.
In the above-described construction, when the rectangular area 2 of X bits laterally and Y bits vertically from the SADD address in the memory space, shown in FIG. 1, is to be moved to the rectangular area 3 of X bits laterally and Y bits vertically Y from DADD address, [SADD] is set at S address register 41 from the central processing unit 13 or the like through S selector 40 and the bit number X is set at X register 44, the bit number Y is set at Y register 46 and [DADD] is stored in D address register 51 through D selector 50, the length P corresponding to one line of the memory unit 1 is stored in SP register 49 and DP register 54 and, where shifting of data is necessary, the shift number is stored in SH register 26 and data transfer is effected.
Thereby, the transfer control unit 10 sets the value of S address register 41 at S address counter 42, the value of X register 44 at X counter 45, the value of Y register 46 at Y counter 47, and the value of D address register 51 at D address counter 52.
Then, the data in the rectangular area 2 shown by the address indicated by S address counter 42 (hereinafter referred to as S-DATA) is first read out and stored in S register 20. Also, the contents of the address in the rectangular area 3 shown by D address counter 52 (hereinafter referred to as D-DATA) is stored in D register 29.
In the data control section 11, the S-DATA stored in S register 20 is shifted by shift unit 25 by an amount designated by SH register 26 as required, and this shifted value and the D-DATA stored in the D register are logically operated in the function unit by the designation of the function register 27. This logically operated data (SD-DATA) and D-DATA are selected by mask register 28 and are output as the data written into the rectangular area 3 from the selector 31, and are written into the address designated by D address counter 52. The masking by the mask register 28 and the shifting by the shift unit 25 are for making part of the read-out D-DATA directly effective when the first and last bit positions of each line of the rectangular area 3 are not coincident with the byte or word boundary of the start bit position of the transferred data from the rectangular area 2. A conceptional view of this case is shown in FIG. 5 of the accompanying drawings. As shown there, the difference in bit position between S-DATA and D-DATA is modified.
Thus, the content of the address shown by S address counter 42 is logically operated in accordance with address shown by D address counter 52, and bit alignment and transfer has been effected. Therefore, S address counter 42 is counted up by the timing circuit 48 and X counter is also counted down by a predetermined number. At the same time, D address counter 52 is counted up by the timing circuit 48. Then, the transfer of the contents of the addresses shown by S address counter 42 and D address counter 52 is effected.
When the transfer of successive data is effected and the transfer of one lateral line is terminated, the X counter 45 becomes "0". By [X counter] =0, a value obtained by adding the value of SP register 49 to the value of S address register 41 with the aid of S adder 43 is stored in S address register 41 through S selector 40 and Y counter 47 is counted down by one. By this process, the first address of the rectangular area 2 of the next line is set at S address register 41. Then the value of this S address register 41 is set at S address counter 42 and the value of X register 44 is again set at X counter 45. Likewise, the values of D address register 51 and DP register 54 are added together by D adder 53 and the sum thereof is stored in D address register 51 through D selector 50, and the value of D address register 51 is set at D address counter 52.
Thus, the transfer of the data of the next line is started.
The above-described process is repeated and when the value of Y counter 47 becomes "0", the transfer of the rectangular area is terminated.
(1) Heretofore, the data transfer, as described above, has only been effected and the content of the rectangular area 2 has been left as is. Therefore, for example, where the memory unit 1 is a display memory such as a display device, when the display corresponding to the rectangular area 2 which is to be transferred to the rectangular area 3, the data of the rectangular area 2 must be newly eliminated after the data transfer has been effected, and this leads to complication of the process increased processing time. PA1 (2) Also, where the rectangular area 2b of the transfer origin and the rectangular area 3b of the transferee have a common memory area, as shown in FIG. 6 of the accompanying drawings, transfer has been impossible and it has been necessary that the data of the rectangular area 2b be once retracted into another memory area and the transfer of data from the other memory area to the rectangular area 3b must be newly effected. PA1 (3) Heretofore, the data transfer as described above has only been effected and for example, a data input from an input device is stored in the rectangular area 2 and when this stored data is to be output to an output device, the data is first transferred to the rectangular area 3 and the output device transfers the data to this rectangular area 3, and the output device effects outputting of the data from this rectangular area 3.
In this case, in the output device, the necessity of outputting the input data while expanding or contracting it sometimes occurs. However, this expansion or contraction process must be effected discretely from the data transfer process with the content of the rectangular area 3 being read out, and this has led to increased processing time and complexity.